Semiconductor device for low voltage protection with low capacitance

ABSTRACT

A semiconductor thyristor device ( 110 ) that incorporates buried regions ( 112 ) spaced around an emitter region ( 114 ). By spacing the buried regions ( 112 ) around the emitter region ( 114 ), current carriers emitted from the buried regions are distributed over a large area of the emitter region ( 114 ), thereby providing a high current capability during initial turn on of the device. In order to achieve low breakover voltage devices, the buried regions ( 112 ) are offset laterally with respect to the respective emitter regions ( 114 ). The low voltage thyristor device exhibits a low capacitance for operating with high speed, low voltage signals. The device capacitance is reduced by utilizing a plurality of buried regions ( 112 ), each formed having a relatively small area junction with the base region ( 118 ).

RELATED APPLICATIONS

[0001] This application is a continuation-in-part of pending U.S.application Ser. No. 09/504,224, filed Feb. 15, 2000, entitled “Very LowVoltage Actuated Thyristor With Centrally-Located Offset Buried Region”,which is a continuation-in-part patent application of U.S. Pat. No.6,084,253, issued Jul. 4, 2000, the entire subject matter of theapplication and patent of which is incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates in general to thyristors and otherfour-layer devices, and more particularly to the fabrication ofthyristor devices having low breakover voltages.

BACKGROUND OF THE INVENTION

[0003] Thyristors, SIDACtor® overvoltage devices and other four-layerdevices are commonly used to provide overvoltage protection to circuitsrequiring the same. The SIDACtor® overvoltage devices are two-terminalthyristors that have bidirectional current carrying capability. Suchdevices are obtainable from Teccor Electronics at many differentbreakover voltage values. When used in conjunction with telephone lines,for example, of the type in which 220-volt ringing signals are carried,a 250-volt breakover voltage SIDACtor® overvoltage device can be used toallow normal operation of the telephone line, but operate at 250 volts,or greater, in response to lightning strikes or power line crosses tothereby safely clamp the line to a very low voltage. This type of adevice provides high surge current capabilities for protecting equipmentfrom damage due to the extraneous voltages that may be coupled to thetelephone line. Five-pin telephone line protection modules utilizingthese high voltage devices have typically been commercially available.

[0004] Many telephone circuits and equipment operate on a 48-volt supplyvoltage. To that end, SIDACtor® overvoltage devices that operate at anominal 64 volts are often used to protect such type of circuits. Anominally operating 30 volt SIDACtor® device can be advantageously usedto protect many 24 volt circuits, such as fire alarm and other systems,that are susceptible to extraneous voltages. It can be appreciated thatthe lines that generally require protection from damage due toextraneous voltages are often in environments where energy fromlightning strikes can be induced into the lines, where high voltage ACcircuits are in close proximity thereto, and for a host of otherreasons.

[0005] While low-voltage digital lines, such as those driven by 5-voltTTL drivers are extensively employed in computerized and otherequipment, such lines have not yet found a large application in outsideinstallations. However, in view of the fact that computer networks andcommunications are increasing at a substantial rate, such low-voltagelines are being used in environments where overvoltage protection isrequired. Such overvoltage protection need not be due solely tolightning and power line crosses, but can be due to other standardvoltages that are commonly found in indoor equipment.

[0006] It is well known in the thyristor and SIDACtor® overvoltagedevice field that the impurity level of a semiconductor wafer can beadjusted to thereby achieve a desired breakover voltage. It is commonlyknown that lightly-doped silicon substrates are characterized by highbreakover voltages. As the doping or impurity level of the substrate isincreased, the breakover voltage is reduced. It is also well known thatthe impurity level of a semiconductor material is inversely proportionalto the resistivity thereof.

[0007] It has also been found that the use of buried regions in thesemiconductor substrate facilitates the operational characteristics of aSIDACtor® overvoltage device. See, for example, U.S. Pat. No. 5,479,031by Webb. Referring to FIG. 1, if the SIDACtor® device is constructed soas to have an N-type emitter 18, a P-type base 16 and an N-typesubstrate 12 or mid-region, a heavily doped P-type buried region 14 canbe implanted between the base region 16 and the silicon substrate 12 tothereby reduce the breakover voltage. Important advantages are achievedwhen the buried region 14 is directly beneath the emitter region 18,with the base region 16 material therebetween. Without significantlychanging the impurity levels of the emitter 18, base 16 and substrate12, the breakover voltage can be changed by simply changing the impuritylevel of the buried region 14. Moreover, in achieving breakover voltagesfrom 250 volts down to 64 volts, the buried region need only be moreheavily doped. In like manner, to achieve 30-volt breakover voltagedevices, the buried region is required to be even more heavily doped.

[0008] As the impurity level of the buried region 14 increases, thejunctions 20-26 formed between the buried region 14 and the base region16 are displaced upwardly toward the emitter region 18. Indeed, as thedoping level of the buried region 14 increases, the distance between theburied region-base junction 20 and the base-emitter junction becomessmaller and smaller. The reason for this is that the junction 20 isformed at a location in the semiconductor material where the donorstates of one impurity are cancelled by the acceptor states of theopposite impurity. Stated another way, the junction of two semiconductormaterials exists where the impurity concentration of one region is equalto the impurity concentration of the other region. The formation of alow breakover voltage SIDACtor® overvoltage device is not an elementarytask.

[0009] It has been found that to fabricate nominal 10-volt breakovervoltage SIDACtor® devices, the impurity level of the buried region mustbe so high that the buried region can often be effectively shortcircuited to the emitter region. In any event, even after fine tuningthe processes so as to prevent short circuiting between the buriedregion and the emitter, the yield of workable devices is low, and thussuch devices become costly.

[0010] Another problem attendant with upward migration of the junctionof the buried region is that the base region under the emitter becomesthinner. The distance in the base region between the emitter junctionand the buried region junction defines, in part, a holding current(I_(h)) parameter. The holding current is that current required tomaintain an on-state of the device. A thinner base region adverselyaffects the ability to control a desired holding current.

[0011] Various other attempts have been made to make low breakovervoltage thyristors. One endeavor involves a semiconductor design inwhich the breakover voltage occurs at the surface of the device. Inother words, the concentration of the impurities at the surface of thedevice is controlled to achieve a low breakdown voltage.

[0012] Standard twisted pair telephone lines are protected by variouscircuits from hazardous voltages and currents that may be imposed on thelines. It is a standard practice to provide primary protection by theuse of five-pin protection modules in the central offices and other highdensity conductor applications. Such modules have a standard pinconfiguration so that the modules of many different suppliers can beinserted into the same type of socket.

[0013] The basic protection to telephone lines includes primaryprotection modules and secondary protection modules. The primaryprotection module provides overvoltage protection against lightningstrikes and power line crosses to the telephone lines. Such primaryprotectors may include gas discharge tubes and other semiconductordevices that can withstand high voltages. Secondary protection circuitsoften include semiconductor devices, resistors, positive temperaturecoefficient devices and other components to provide lower voltageprotection to the customer side equipment. A family of overvoltageprotection SIDACtorg® devices providing the secondary protection isavailable from Teccor Electronics, Irving, Tex. The primary protectionmodule is effective to limit the hazardous line voltages toapproximately 300 volts. The secondary protection circuits, for examplein line cards, provide additional protection to the telephone lines atlevels below 300 volts.

[0014] While numerous five-pin primary protection modules arecommercially available to provide primary protection, there is a limitedselection of five-pin secondary protection modules providing secondaryprotection.

[0015] Recent changes in regulatory requirements suggest the use of DCisolation as well as overvoltage protection in secondary protectioncircuits of certain types of equipment. This imposes additionalconstraints not currently satisfied by currently available devices andcircuits.

[0016] From the foregoing, it can be seen that a need exists for amethod and technique to fabricate low breakover voltage thyristordevices. Another need exists for a technique to fabricate low voltagethyristor devices where the breakover voltage is independent of theholding current. Yet another need exists for a thyristor device whichcan be reliably made with high yields, thereby reducing the cost of thedevices. Another need exists for a five-pin communication lineprotection module for use with low voltage communication lines. Afurther need exists for a low voltage thyristor device that exhibits alow voltage overshoot in response to fast rise time transients, and thatexhibits a low device capacitance.

SUMMARY OF THE INVENTION

[0017] In accordance with the principles and concepts of the invention,there is disclosed a technique for fabricating low-voltage thyristordevices, which technique overcomes the disadvantages and shortcomings ofthe prior art.

[0018] In accordance with an edge-fired embodiment of the invention, theburied region is laterally offset from the emitter region. The upwardmovement of the buried region junction as a function of the impuritylevel does not thereby interfere or otherwise become too close to theemitter junction. In addition, because of the lateral displacement ofthe buried region from the emitter, the base region underlying theemitter does not vary in thickness as a function of the location of theburied region junction. This essentially makes the breakover voltageindependent of the holding current value of the device.

[0019] In accordance with another feature of the invention, a deep baseis provided to thereby make the mid-region of the substrate thinner. Themid-region of the substrate functions in the four-layer device as a baseof one of the regenerative-connected transistors of the thyristordevice. With a thinner transistor base, the gain of the device ishigher, thereby allowing the thyristor device to remain in an on statewith a lower holding current.

[0020] In another embodiment, a four-layer thyristor is fabricatedutilizing a pair of spaced apart emitters with the buried regiondisposed therebetween.

[0021] In yet another embodiment, a low voltage thyristor device isformed as a center-fired device in which the buried region is formedoffset from the emitter, but generally centered in the chip. Thisarrangement not only allows an increased device current to flow, butalso facilitates assembly of the packaged device. By placing the buriedregion in the center of the semiconductor chip and utilizing twosymmetrically oriented metal contacts, the chip self centers itself to alead frame when reflow soldered thereto.

[0022] In yet another embodiment, a five-pin communication lineprotection module uses the low-voltage thyristor to provide low voltageline protection to other circuits, such as data systems.

[0023] According to another embodiment, high impurity concentrationburied regions are used to not only achieve a low breakdown voltage, butthe buried regions are constructed utilizing cross-sectionally smallareas to reduce device capacitance. The device can thus be used forprotecting lines carrying high speed digital signals. An additionalfeature of this embodiment is that the buried regions are formed atvarious locations with respect to the emitter region, such that fullconduction over the entire emitter area is achieved faster, therebyreducing the voltage overshoot of the device. In accordance with adescribed embodiment, the emitter of the device is fabricated with aperipheral edge or perimeter having indentions or cutouts formedtherein. Formed below such cutouts are corresponding buried regions. Thelocation of the buried regions with respect to the emitter allowcarriers emitted from the buried regions to flow to essentially theentire, if not all, of the emitter area, thereby providing full turn onof the emitter. This allows high current densities to be accommodatedduring turn on of the device without causing “bottle-neck” locations ofthe current.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Further features and advantages will become apparent from thefollowing description of the drawings, in which like referencedcharacteristics generally refer to the same parts, elements or functionsthroughout the views, and in which:

[0025]FIG. 1 is a cross-sectional view of a low breakover voltageSIDACtor® device constructed in accordance with the prior art;

[0026]FIG. 2 is a cross-sectional view of a low voltage SIDACtor® deviceconstructed in accordance with one embodiment of the invention;

[0027]FIGS. 3 and 4 are respective cross-sectional and top views of yetanother embodiment of a low voltage SIDACtor® device having a deep baseregion to effectively make the mid-region of the substrate thinner,thereby reducing the holding current characteristics of the device;

[0028]FIGS. 5 and 6 are respective cross-sectional views of a lowvoltage SIDACtor® device utilizing a buried region disposed betweenemitter regions;

[0029]FIG. 7 is a cross-sectional view of a low voltage SIDACtor® deviceutilizing a base region that has a portion thereof that is lightly dopedfor improved turn-on performance, and a more heavily doped portion ofthe base region to control the breakover voltage;

[0030]FIGS. 8 and 9a are respective top and sectional views of yetanother embodiment of the invention, in which the device is considered a“center-fired” device in that the buried region is centrally located inthe semiconductor chip;

[0031]FIG. 9b is a cross-sectional view of another embodiment of theinvention with semiconductor areas formed so that the entire devicefunctions as a low voltage Zener diode;

[0032]FIG. 10 is a side view of a thyristor device soldered to leadframe members;

[0033]FIGS. 11 and 12 are respective circuit diagrams of low voltagecommunication line protection circuits;

[0034]FIGS. 13 and 14 are five-pin protection modules embodying therespective low voltage protection circuits shown in FIGS. 11 and 12;

[0035]FIG. 15 is an isometric view of a five-pin protection moduleutilizing low-voltage protection circuits;

[0036]FIG. 16 is a top view of another embodiment of the invention,showing the features of the individual buried regions, as well as thelocation of the buried regions with respect to the emitter;

[0037]FIG. 17 is a cross-sectional view of the device of FIG. 16, takenalong line 17-17 thereof;

[0038]FIG. 18 is a cross-sectional view of the device of FIG. 16, takenalong line 18-18 thereof;

[0039]FIG. 19 is a top view of the device of FIG. 16 subsequent to ametalization of the chip;

[0040]FIG. 20 is a top layout view of the device of FIGS. 16-19, showingthe pattern of carriers emanating from each buried region;

[0041]FIG. 21 is a top layout view of another embodiment similar to thatof FIG. 16, but employing a larger emitter and thus more buried regionsfor providing carriers thereto;

[0042]FIG. 22 is a cross-sectional view of the device of FIG. 21, takenalong line 22-22 thereof;

[0043]FIG. 23 is a cross-sectional view of the device of FIG. 21, takenalong line 23-23 thereof;

[0044]FIG. 24 is a top layout view of the device of FIG. 21, showing thepattern of carriers emanating from each buried region;

[0045]FIG. 25 is a top view of another embodiment of the invention wherethe buried regions are located under corresponding openings in theemitter region;

[0046]FIG. 26 is a sectional view of the device of FIG. 25, taken alongline 26-26 thereof; and

[0047]FIG. 27 is a top view similar to that of FIG. 25, but with brokenlines showing the emanation of carriers from the buried regions.

DETAILED DESCRIPTION OF THE INVENTION

[0048]FIG. 2 illustrates the principles and concepts of one embodimentof the invention. A single four-layer unidirectional device 30 isillustrated. Two such devices (a top surface and bottom surface device)can be formed in the semiconductor substrate to provide bidirectionalcurrent flow capabilities. The device 30 is formed in the top surface ofa starting silicon substrate 32 of the P-type. Region 32 defines boththe mid-region of the four-layer thyristor, and a base of a PNPtransistor. An N-type base region 34 for one device is formed in the topsurface of the wafer, and a second N-type base region 36 for a seconddevice (not shown) is formed in the bottom surface of the wafer. Aheavily doped buried region 38 is formed in the substrate 32, preferablyby standard semiconductor diffusion techniques and before either baseregion 34 or 36 is formed. The buried region 38 is formed by depositingboron ions for about three days, resulting in a surface concentration ofabout 10 ¹⁹ atoms per cm³, and at a depth of 80 microns. This impurityconcentration at the top of the buried region 38 is effective to providea breakover voltage in the range of 8-12 volts. The wafer undergoes thediffusion process at a temperature of about 1275° centigrade for aboutthree days to activate the ions. After activation, a buried regionjunction 40 is formed in the base region 34. A P-type emitter region 42is formed in the base region 34, but offset laterally from the buriedregion 38. A metal emitter contact 44 is formed in electrical contactwith both the emitter region 42 and the base region 34. On thesemiconductor wafer overlying the buried region 38, there is formed adielectric layer 46 of glass, oxide or other electrically insulatingmaterial.

[0049] As can be seen from FIG. 2, the buried region 38 does notunderlie the emitter region 42. Rather, the buried region 38 is offsetso that the junction 40 with the base region 34 does not come into closevertical proximity to the emitter-base junction, even when the buriedregion junction 40 becomes increasingly shallow as the buried region 38becomes more heavily doped. Any upward movement of the buried regionjunction 40 is due to the application of high processing temperatures(1275° C.) to activate the P-type ions. Indeed, even when the buriedregion junction 40 becomes extremely shallow due to the heavy doping ofthe buried region 38, there is no possibility that it would shortcircuit with the emitter-base junction. The arrangement of thesemiconductor regions of FIG. 2 defines an edge fired thyristor device,in that the buried region 38 is located near the edge of the chip. Theburied region associated with the companion unidirectional device (notshown) in FIG. 2 would be located near the bottom left of the chip, muchlike the positions of the buried regions shown in the prior art deviceof FIG. 1.

[0050] The holding current I_(h) of the device 30 is a function of thedistance 52 between the emitter-base junction 48 and the base andmid-region junction 50. As can be appreciated, the distance 52 isindependent of the location of the buried region junction 40.

[0051] The breakover voltage (V_(B0)) of the device 30 is primarily afunction of the distance 54 between the buried region junction 40 andthe upper surface 56 of the semiconductor wafer. In addition, and asnoted above, the impurity concentration of the buried regions 38 alsodetermines the breakover voltage characteristics of the device 30. Inaccordance with an important feature of the invention, the breakovervoltage of the device 30 is determined, in part, by the distance 54,which is independent of the holding current characteristics. The holdingcurrent characteristics are determined primarily by the distance 52. Notonly can a high impurity concentration buried region 38 be used withoutthe attendant problem of short circuiting with the emitter-base junction48, but the device made according to the invention renders the breakovervoltage characteristics independent of the holding currentcharacteristics.

[0052] As noted above, an insulating dielectric 46 overlies the buriedregion 38. The reason for this is that when the device is subjected toan overvoltage, initial breakdown occurs as current flows from thebottom base region 36 to the emitter 42, via the buried region 38. Withmultiple buried regions, multiple current paths are initially formed,thereby providing a high surge current capability. To force the initialcurrent during breakdown to pass through the emitter region 48 andthrough the emitter contact 44, the base region above the buried region38 is covered with the insulator 46. Otherwise, if the metal contact 44extended over the buried region 38, current would bypass the emitterregion 42 and pass directly to the emitter contact 44. Once the currentthrough the device 30 reaches the switching current (I_(s)), theon-state of the device is maintained and current flow need not passthrough the buried region 38. It can be appreciated from the foregoingthat the lateral distance between the emitter region 42 and the buriedregion 38 should be small to increase the turn-on speed of the device,as well as to reduce the initial overshoot during turn on. In thefabrication of a bidirectional SIDACtor® device, two devices (one shownin FIG. 2) can be used, one formed in the top surface of the substrate,and the other device formed in the bottom surface.

[0053]FIG. 3 illustrates another embodiment 60 of the invention havingdouble base regions formed on the top surface of the substrate, anddouble base regions formed on the bottom surface of the substrate. Inthe example shown, the substrate or mid-region 62 is employed, and oneor more buried regions 64 are formed therein in the manner noted abovewith reference to FIG. 2. A first thick base region 65 is formed in thetop surface of the substrate, and doped with an N-type impurity toachieve an 80 ohm per square resistivity. A second thinner base region66 is formed in the first base region 65. The base region thicknessesare not shown to scale in the drawings. The second base region 66 isformed at a higher N-type impurity level at the surface of about 3×10¹⁹atoms per cubic centimeter. The heavily doped N-type base region 66 andthe heavily doped P-type buried region 64 allow a junction to be formedtherebetween. In the top base 66 there is formed a P-type emitter 68.Again, the buried region 64 is laterally offset with respect to theemitter region 68, thereby making the breakover voltage characteristicsindependent of the holding current characteristics. In addition, byutilizing a double base region in the top and bottom surfaces of thesubstrate 62, the mid-region 62 is thereby effectively narrowed. TheP-type mid-region 62 corresponds to the base of an NPN transistor whichforms one-half of the thyristor device. By making the mid-region 62thinner, and thus the base region of the NPN transistor thinner, thegain of the device is improved and the initial breakover characteristicis improved to reduce the overshoot. Overshoot is considered to be apositive current/voltage slope of the device once breakover (V_(B0))begins to occur. FIG. 4 is a top view of the device 60, taken along line4-4 of FIG. 3.

[0054]FIGS. 5 and 6 illustrate another embodiment of a thyristor device70 in which the emitter configuration is modified. Here, a pair ofspaced-apart P-type emitters 72 and 74 are formed in the N-type baseregion 76. Indeed, each emitter region 72 and 74 is spaced on each sideof the buried region 78. As noted in the next step of the process shownin FIG. 6, additional P-type impurities are diffused into the topsurface of the base region to form a bridge 80 that thereby shortcircuits the emitters 72 and 74 together. The bridge 80 should besufficiently thin to maintain a separation with the junction 86 of theburied region 78. The bottom surface of the junction 82 of each emitterregion 72 and 74 can thus be formed as close to the junction 84 asnecessary, to improve the gain and turn-on characteristics of thedevice. Again, the distance between the junction 82 and the junction 84is independent of the location of the junction 86 formed at the top ofthe buried region 78.

[0055] With reference now to FIG. 7 there is illustrated anotherembodiment 90 of the invention. Here, there is shown a P-type mid-region92, an N-type base region 94 and a P-type emitter 96 formed therein. Thefirst base region 94 is highly doped and underlies the emitter region96. Disposed laterally at the side of the emitter 96 is a more heavilydoped second base region 98. A buried region 100 forms a junction 102 inthe heavily doped second region 98. Since the more heavily doped baseregion 98 does not underlie the emitter 96, the turn on characteristicsof the device are not substantially affected. With this arrangement, thebreakover voltage can be reduced further, thus providing overvoltageprotection to low voltage communication lines.

[0056] Another embodiment of the invention is shown in FIGS. 8 and 9a.This thyristor device 110 also includes a buried region 112 that islaterally offset with respect to an emitter region 114. Rather thanplacing the buried region 112 near an edge of the chip, the buriedregion 112 is located generally in the central portion of the chip. Aswill be described in more detail below, the center-fired design allowsthe metal contact areas to be larger, thereby providing a largercurrent-carrying capability. Two symmetrically-oriented surface contactsare located on each side of the wafer, thereby allowing easier centeringof the device within a lead frame during assembly of the packageddevice.

[0057] The thyristor device 110 shown in FIGS. 8 and 9 includes a firstbase region 116 and a second base region 118, providing the sameadvantages noted above in connection with the embodiment of FIG. 3. Ametal cathode contact 120, such as solder, is formed in electricalcontact with the emitter region 114. The solder contact 120 is boundedby silicon oxide 122. Formed at the same time as the central buriedregion 112 is another buried region 124 formed at the edge of the chip.The buried region 124 functions to terminate the junction of the twobase regions 116 and 118. An insulating material, such as glass 126,formed in a trench serves to prevent the edge-located buried region 124from initiating conduction of carriers toward the emitter 114. Rather,electron conduction is initiated through the central buried region 112.

[0058] One unidirectional device of the thyristor involves the centralburied region 112, the emitter 114, the upper two base regions 116 and118, the mid-region 127, as well as the lower two base regions 128 and130. A lower contact 132 functions as the anode to the firstunidirectional device of the thyristor 110. Assuming the thyristor 110is biased so that the cathode contact 120 is positive with respect tothe anode contact 132, electron current flows from the anode 132 throughthe bottom base regions 128 and 130, through the mid-region 127 and intothe central buried region 112. Initial electron current does not flowdirectly through the upper base regions 116 and 118, but first throughthe central buried region 112. From the top junction 134 of the buriedregion 112, electrons flow into the upper N2 base region 118 and intothe emitter region 114, whereupon thyristor conduction begins. Currentflows from the emitter region 114 and out of the cathode contact 120.Once conduction is initiated by way of the central buried region 134,current thereafter flows directly from the mid-region 127 through theupper N1 and N2 base regions 116 and 118 into the emitter 114.

[0059] The glass-filled trench insulation regions 126 and 136 functionto prevent initiation of current flow, except through the central buriedregion junction 134 to the emitter 114. The glass-filled trench 136prevents initial electron current from flowing through the centralburied region 112 into a metal anode contact 137 formed in the topsurface. This is because the breakdown voltage of the top junction 134of the central buried region 112 is lower than the breakdown voltage atthe side junction indicated by reference numeral 138. The breakdownvoltage of the side junction 138 of the buried region 112 under theglass 136 is greater than that of the top junction 134. The reason forthe difference in breakdown voltages is that the impurity concentrationof the buried region 112 at the side junction 138 is less than that atthe top junction 134. As noted above, the heavily doped central buriedregion 112 is formed by a long-term diffusion process which naturallyresults in an impurity concentration gradient between the upper andlower portions of the central buried region 112. According to thediffusion process, the impurity concentration of the upper part of thecentral buried region 112 is greater than the impurity concentrationlocated therebelow. With a lower impurity concentration at the sidejunction 138, the breakdown voltage is naturally higher than that at thetop junction 134. As a result, the top junction 134 of the centralburied region 112 reaches breakdown first, whereupon initial electroncurrent flow is through the top of the central buried region 112 to theemitter 114. The same principle operates in conjunction with the edgeburied region 124 and the glass-filled trench 126. It is noted that thedepth of the glass-filled trench boundaries 126 and 136 are formed atthe same depth. Indeed, the insulating glass 126 and 136 are formedabout the periphery of the device, and formed at the same time in asingle peripheral trench.

[0060] In the event it is desired that a higher switching current beachieved in the device, the depth of the glass 136 can be less, therebyraising the upper edge of the side junction 138, thus reducing thebreakdown voltage at that location. With a lower breakdown voltage, somecurrent tends to pass from the central buried region 112 into the leftN2 region 148 and out the metal anode contact 136. As will be describedmore fully below, the top metal contacts 120 and 137 are short circuitedtogether by a lead frame, and the lower contacts 132 and 140 are shortcircuited together by another lead frame.

[0061] The other bidirectional device of the thyristor 110 includes abottom emitter 142 in contact with the bottom cathode contact 140. Thetwo lower base regions 144 and 146 are associated electrically with theemitter 142. The upper two base regions 148 and 150 are associated withthe anode contact 137. Current flow in the second bidirectional deviceis from the anode contact 137 to the cathode contact 140. As with theother unidirectional device described above, initial electron currentflows from the anode contact 137 through the two upper base regions 148and 150, through the mid-region 127 and into the lower, central buriedregion 152. Electron current flows out of the bottom-most junction 154of the buried region 152, through the heavily doped lower base region144 and into the emitter 142. Once conduction is initiated, current doesnot pass through the buried region 152, but rather through the lowerbase regions 144 and 146 into the emitter 142 and out of the cathodecontact 140. The various insulator glass and silicon oxide regions shownformed in the bottom of the semiconductor chip 110 provide the samefunction as those described above in connection with the top of thesemiconductor chip 110. As can be appreciated, if the overvoltage towhich the thyristor device 110 is subjected is an AC signal, then theunidirectional devices will conduct alternately based on the positiveand negative cycles of the AC signal.

[0062]FIG. 9b illustrates an embodiment of the invention that functionsin a manner similar to a low voltage Zener diode. The semiconductorregions formed in the right-most part of the semiconductor chip 156function in the same manner noted above to produce an overvoltageprotection device when a negative voltage is applied to the bottomcontact 158 and a more positive voltage is applied to the top contact120. When the voltage applied across the device is reversed, thesemiconductor regions on the left function as a diode bridged across theother unidirectional device. The N-type regions 148 and 150 togetherwith the P-type regions 127 and 142 define the diode. In thisembodiment, only a single bottom contact 158 is necessary.

[0063]FIG. 10 is a side view of the thyristor device 110 as assembled inconnection with a first lead frame 160 and a metal preform 162. As canbe seen, the top cathode contact 120 and top anode contact 137 aresoldered to the top preform 162, and thus short circuited together. Inlike manner, the bottom anode contact 132 and bottom cathode contact 140are soldered to the bottom lead frame 160 and are thereby shortcircuited together. The top preform 162 is soldered to an up-turned end164 of a second lead frame 166. The joint 168 between the second leadframe 166 and the preform 162 is reflow soldered at the same time as thesolder contacts of the thyristor device 110 are reflow soldered to therespective preform 162 and first lead frame 160. Due to the surfacetension inherent in the liquified solder, the edge 170 of the first leadframe 160 tends to become self-aligned with the edge of the bottom anodecontact 132. Similarly, the edge 172 of the preform 162 tends to becomeself aligned with the edge of the soldered anode contact 137. This selfcentering of the thyristor device with respect to the first lead frame160 and the preform 162 helps prevent misalignment of the device withrespect to the lead frames and thus increases assembly yield of theresulting semiconductor structure. Were it not for the symmetry betweenthe edges of the various solder contacts of the thyristor device 110 andthe lead frames, registration of the components would be more difficult.In the event that the thyristor device 110 becomes misaligned with thelead frames, the assembly will not correctly fit into the mold for finalpackaging and encapsulation of the device.

[0064] As noted above, another advantage of the symmetry between the topsolder contacts 120 and 137 and the bottom solder contacts 132 and 140is that larger area contacts can be formed to thereby facilitateincreased current capability of the device. This symmetry can beachieved because the buried regions 112 and 152 are formed in verticalalignment. In practice, it has been found that the effective conductionarea of the metallized emitter of FIG. 2 was about 883 square mils (0.57mm²), whereas the corresponding area of both top contacts of theembodiment shown in FIG. 8 is about 1111 square mils (0.72 mm²).

[0065]FIG. 11 illustrates a five-pin, low voltage communication lineprotection circuit for providing twenty volt protection to circuits (notshown) connected to the customer tip and ring conductors. The protectioncircuit is useful in providing low voltage protection to telephonesignaling lines that are typically employed to report alarms and thestatus of banks or series of printed circuit cards. These signalinglines constitute private communication channels used to communicatebetween a central office and remotely located terminals or cabinets.Such lines are not powered by the standard 48 volt supply but rather arelow voltage operating circuits.

[0066] The tip conductor 179 is connected in series with a positivetemperature coefficient (PTC) element 180 to the customer tip conductor185. The PTC element 180 produces about 4-10 ohms resistance up to about300 ma flowing therethrough. Should the tip line current increase, theresistance of PTC element 180 increases to provide overcurrentprotection to the customer side circuits. When the tip line current isreduced, the resistance of the PTC element 180 returns to its originalvalue. Bridged between the customer tip conductor 185 and ground 181 isa twenty-volt Zener diode 182. A small value capacitor (470 pF) 184functions to filter, condition and stabilize the signal line. Theoutside ring conductor 183 is similarly situated, in that it isconnected in series with a PTC element 186 to the customer ringconductor 187. A second Zener diode 188 provides twenty volt protectionto the customer ring equipment. The Zener diodes 182 and 188 can be ofthe type shown above in conjunction with FIG. 9b. A capacitor 190provides the same function to the ring conductor 183 as capacitor 184provides to the tip conductor 179.

[0067] While the low voltage protection circuit of FIG. 11 uses Zenerdiodes 182, 188, the four-layer devices described above in connectionwith FIGS. 1-9 a can be used with equal effectiveness in place of theZener diodes 182, 188. Zener diodes can be fabricated by maintainingonly a single unidirectional device as described above in connectionwith FIG. 9b, and replacing the other unidirectional device with aneffective PN junction. Those skilled in the art can readily appreciatethe manner in which the various semiconductor regions can be modified bymasking and diffusion techniques to provide a diode in parallel with theother unidirectional thyristor device.

[0068] When packaging or otherwise implementing the circuit of FIG. 11in a module, it is not necessary to use the entire circuit. Rather, whenit is desired to protect only the customer tip conductor 185 fromhazardous voltages appearing on the outside tip conductor 179, then thecapacitor 190 and Zener diode 188 can be omitted. Only a three-pinmodule may be necessary in this instance to provide protection to oneline or conductor. The converse is also true if hazardous voltageprotection is necessary to only the customer ring conductor 187.

[0069]FIG. 12 illustrates yet another embodiment of a low voltageprotection circuit that uses a transformer 196. Such an arrangement canbe employed for connection to standard T1 or E1 digital transmission, ormany other types of lines. In this embodiment, the tip conductor 191 isconnected through a PTC element 192 through the primary 194 of thetransformer 196. The other terminal of the transformer primary 194 iscoupled through another PTC element 198 to the ring conductor 193. Thetransformer secondary 200 has one terminal connected to a customer tipconductor 195, and another terminal connected to a customer ringconductor 197. Connected between the customer tip conductor 195andground 201 is a back-to-back Zener diode arrangement 202 providingbidirectional protection in the neighborhood of about 6.8 volts to thecustomer tip conductor 195. A second bidirectional Zener diodearrangement 204 is coupled between the customer ring conductor 197 andground 201 to provide bidirectional protection to the customer ringconductor 197.

[0070] The transformer 196 is effective to block any DC voltage that mayexist on the tip and ring conductors from entering the customercircuits. Some T1 and E1 transmission lines can be powered by 130 voltor 48 volt supplies. The transformer prevents such DC voltages frombeing coupled to the lower operating voltage equipment of the customer.However, any AC voice, pulse or other similar types of signals are ableto be transferred from the transformer primary 194 to the transformersecondary 200 and coupled to the customer circuits. The electricalisolation and other parameters provided by the transformer 196 may be ofthe type satisfying the recognized standards of UL 497A, CSA C22.2 NO.950-95 and UL 1950 (3rd edition).

[0071] The line conditioning and protection circuit of FIG. 12 is welladapted for those situations where the outside line conditions are notwell identified or known, and where the protection of the inside orcustomer circuits is important. For example, where there may be numerouslines incoming from various destinations and different applicationswhere the electrical properties, operating conditions andcharacteristics of the lines may not be known, the protection module orcircuit of FIG. 12 can be used to isolate all external DC voltages fromthe customer circuits but still allow the AC information to betransferred. The interfacing of the many outside lines to the customercircuits can be achieved by utilizing a bank of five-pin sockets, whereeach socket has pins connected to the outside lines, the customer lines,and a ground connection. A module with a protection circuit such asdescribed above can be plugged into the socket to provide the type ofprotection desired. If different lines require different types ofelectrical protection, then a module with a different circuit thereincan be used. The modules can be color coded or otherwise visuallydistinguished to identify the different circuits therein.

[0072] The modularized line conditioning and protection circuits canfacilitate compliance with new or modified standards and specifications.In those situations where there already exists the primary and secondaryprotection circuits, the circuits shown in FIGS. 11 and 12, and yetother circuits, can be incorporated with the existing protectioncircuits to establish compliance with the new standards orspecifications. The integration of the new protection circuits can befacilitated by incorporating the same into modular form adapted forplugging into standardized sockets. The adaptation of the new circuitscan even be achieved in these instances by incorporating the standardsecondary protection circuits with the new conditioning and protectioncircuits into the same module, and plug such module into the socket thatpreviously held the standard secondary protection module. This featureallows the incorporation of the new protection scheme without having towire, rewire or make connections to the existing communication lines.

[0073] The low voltage protection circuits of FIGS. 11 and 12 can beincorporated into five-pin modules for easy use and plugability intocustomer communication interface equipment. With reference to FIG. 13,there is illustrated the telephone line protection circuit of FIG. 11assembled in a five-pin module structure 206. The five pins 210 of themodule are arranged in a standard configuration well known in the art.The pins 210 are fixed within a plastic molded base 212. A first printedcircuit board 214 has conductive paths soldered to the respective pins210. A second printed circuit board 216 is fabricated to hold theelectrical components shown in FIG. 11. Various wire conductors 218 and220 serve to connect the various conductors of the second printedcircuit board 216 to the first printed circuit board 214 so that thecircuit configuration operates electrically as shown in FIG. 11. Theconductors 220 also support the second printed circuit board 216vertically with respect to the first printed circuit board 214. Aplastic molded cover 222 (FIG. 15) is molded to snap fit to the base 212by way of the small openings 224 formed in the cover. The openings 224are snap fit around corresponding bosses 216 extending from sides of themodule base 212. As noted above, the Zener diodes 182 and 188 can beused as the low voltage thyristor devices described above, and packagedin diode-shaped packages. Other package configurations, including thewell-known TO style packages can be easily soldered to the printedcircuit boards.

[0074] With reference now to FIG. 14, there is illustrated a five-pinmodule 228 incorporating the components of the low voltage protectioncircuit of FIG. 12. Again, there is a standard configuration five-pinmolded base 230 to which the five pins 232 are fixed. A first printedcircuit board 234 has conductive paths soldered to the respective pins232. A second upright printed circuit board 236 is wired to the firstprinted circuit board 234 by a number of wire conductors 238 and 239.One terminal of each PTC element 192 and 198 is connected to therespective conductive paths of the second printed circuit board 236,while the other respective terminals 238 and 240 are connected directlyto the first printed circuit board 234. The various printed circuitboard conductive paths and components shown in FIG. 14 are arranged toprovide the functions of the electrical circuit shown in FIG. 12.

[0075]FIG. 15 illustrates a completed low voltage five-pin protectionmodule 206 that may house the components of either circuit shown in FIG.13 or FIG. 14. A finger-grip handle 242 molded as part of the cover 222permits easy installation or replacement of the low voltage protectioncircuits in the customer equipment racks. The standard five-pin moduleconfiguration can be used to provide low voltage protection to varioustypes of customer equipment that operates with low voltage signalscarried on the lines. Indeed, the low voltage protection circuits anddevices described above need not provide protection to voltages to whichstandard twisted pair telephone lines may be exposed, but rather toother digital and low-level signal lines that may never be exposed tolightning or power line voltages. Rather, many types of digital andanalog communication lines may require protection from inside powersources, such as DC or AC power supplies which may be inadvertentlycoupled to the customer equipment, or where other circuits fail andallow damaging voltages between 5-50 volts to be coupled to the customerequipment. The various devices, circuits, modules and combinationsthereof can be adapted for use with these and many other applications.

[0076] FIGS. 16-20 illustrate yet another embodiment of the invention,where plural buried regions are selectively located at different sitesin the overvoltage protection device 250, thereby allowing currentcarriers to quickly migrate to substantially the entire surface area ofthe emitter region 258 during initial turn on of the device 250. In thefabrication of the device 250 according to this embodiment, a siliconwafer uniformly doped with a P-type impurity is used as the startingsemiconductor material. The starting silicon material forms a mid-region252 of the device 250. Those skilled in the art may prefer to use astarting silicon wafer of an N-type, in which event the polarities ofthe various semiconductor regions described below would be reversed.

[0077] The P-type silicon mid-region 252 is then masked to definecircular openings for forming the various buried regions deep into themid-region 252. In accordance with an important feature of theinvention, the number of buried regions formed within the siliconmaterial corresponds generally to the area of the emitter region 258.For larger emitter regions in terms of lateral area, either larger areaburied regions or more buried regions may be used. While the use of manyburied regions may increase the turn-on speed of the device, the overallcapacitance of the device is also increased. A compromise must generallybe made between the turn-on speed of the device, and the capacitance ofthe device.

[0078] In one embodiment, the device 250 is formed on a squaresemiconductor chip having an area of about 75.0 mils square. The area ofthe emitter region 258 is about half the area of the device 250. In anyevent, each current-carrying device on the chip using this configurationis fabricated with four buried regions. Two buried regions 254 and 256are formed somewhat adjacent to each other, close to the outside edge ofthe chip, adjacent to and laterally offset with respect to the emitterregion 258. Importantly, the breakdown junction of each buried region isformed laterally offset from the emitter region. The breakdown junctionof the buried regions means the portion of the junction that generallydefines the breakover voltage of the overvoltage protection device.

[0079] Two other buried regions 260 and 262 are formed further apart,adjacent the opposite edge of the emitter region 258. The buried regions260 and 262 are formed adjacent two respective comers of the emitterregion 258. As will be described more thoroughly below, this pattern orlocation of buried regions enhances the turn-on speed of the device 250and thus lowers the voltage overshoot. This is critically important inthe fabrication of overvoltage protection devices having low breakovervoltage characteristics, namely fifty volts and below. As noted above,such type of overvoltage protection devices are useful in protectingdigital or other low-voltage telecommunication lines or conductors.

[0080] The openings in the mask for forming the buried regions 254, 256and 260, 262 are circular in shape and located in the positions shown inFIG. 16. In the processing of a wafer having many chip areas thereon,the various masking and deposition steps are carried out on both sidesof the wafer at the same time. The mask opening forming each buriedregion has a radius of about 2.0 mils. A P-type impurity is deposited onthe wafer, in the openings, with a concentration sufficient to achievethe desired breakdown voltage suitable for protecting lines on whichdigital signals are transmitted. In order to achieve a breakover voltageof about ten volts, a P-type impurity, such as boron, is deposited tosubstantially a saturation level. Next, the boron atoms are drivendeeply into the wafer from both sides thereof to a depth of about3.0-3.5 mils, as shown in FIGS. 17 and 18. The deep buried regions areformed by subjecting the wafer to a temperature of about 1275° C. forabout 72 hours. It can be appreciated that both sides of the wafer areprocessed at the same time to form buried regions in the shape andlocation as noted in FIGS. 16-18. The device 250 has formed therein oneovervoltage protection device (with four buried regions) for conductingcurrent in one direction, and a counterpart overvoltage protectiondevice (with four other buried regions) for conducting current in theopposite direction. The processing steps and the geometry of eachovervoltage protection are substantially identical. A bidirectionalovervoltage protection device 250 for protecting circuits fromovervoltages of either polarity is thus provided.

[0081] With reference now to FIGS. 17 and 18, the wafer is masked onboth sides thereof to form openings in which a well or tub of N-typeimpurities are diffused. N-type impurities such as phosphorus can beused. The n-wells 264 and 266 are formed directly underlying surfacelocations at which the respective emitter regions will be formed. Therespective top and bottom wells 264 and 266 function to reduce theeffective thickness of the mid-region 252 and increase the switchingspeed of the device 250. With a thinner mid-region, the forward turn-onvoltage of the device is reduced.

[0082] Subsequent to the formation of the n-wells 264 and 266, the waferis prepared to form a pair of first base regions 268 and 272 inrespective sides of the wafer. The wafer is not masked when forming thebase regions. The first base region 268 is lightly doped to form an80-ohm N-type layer, and is formed so as to be contiguous with then-well 264. The first base region 268 is formed by depositing an N-typeimpurity (such as phosphorus) into the surface and diffusing theimpurity atoms to a depth substantially as shown in FIGS. 17 and 18.Because of the inherent characteristics of the high temperaturediffusion process, an impurity gradient is formed in the first baseregion 268. The gradient of the N-type impurities in the first baseregion 268, together with the heavily doped P-type buried regions,define a frustoconical-shaped junction 270 around a portion of eachburied region. A similar first base region 272 is formed in the oppositeside of the wafer contiguous with the respective n-well 266. Thelightly-doped first base region 272 also forms a frustoconical-shapedjunction 274 with respect to the buried regions 257 associated with thecounterpart overvoltage protection device.

[0083] In the next step of the process in fabricating the device 250, asecond, or upper, base region 276 is formed over the first base region268. A second base region 278 is also formed on the opposite side of thewafer, over the other corresponding first base region 272. Inparticular, the second base regions 276 and 278 are formed with a highconcentration of N-type impurities. The second base regions 276 and 278have sufficiently high concentrations such that the upper sections ofthe respective buried regions 256 and 257 become inverted, therebyresulting in a layer of N-type impurities in the second base regions 276and 278. While only two buried regions are illustrated for eachovervoltage protection device in FIGS. 17 and 18, all four buriedregions of each device undergo the same processing. As a result of suchprocessing, a breakdown junction 280 is formed at the interface betweenthe top lateral surface of the buried region 256 and the second heavilydoped base region 276. A similar breakdown junction 282 is formed withrespect to the buried region 257 and the second base region 278 formedin the opposite side of the device 250. These junctions of the buriedregions define the breakover voltage of the overvoltage protectiondevices. Importantly, these breakdown junctions are formed laterallyoffset from respective portions of the emitter region. It is generallyinconsequential if other portions of the buried regions formingrespective high breakdown voltage junctions with the lightly doped baseregions are formed under the emitter regions. The heavily doped secondbase regions 276 and 278 effectively “bury” the respective buriedregions 256 and 274, as well as the other buried regions (not shown)formed in the top and bottom surfaces of the wafer.

[0084] Respective emitter regions 258 and 286 for each overvoltageprotection device are next formed in the opposing sides of the device250. As shown in FIG. 17, the top emitter region 258 is formed laterallywith respect to the buried region 256. In like manner, the bottomemitter region 286 is formed laterally with respect to the correspondingburied region 257. Each buried region is similarly offset with respectto the associated emitter regions. The offset nature of the breakdownjunctions of the buried regions, and the respective emitter regionsprovide the same advantages as noted above in connection with the otherembodiments of the invention. Importantly, as illustrated in FIG. 16,the emitter region 258 is formed around at least a portion of eachcircular-shaped buried region. With this arrangement, no portion of theemitter region 258 overlies any of the corresponding breakdown junctionsof buried regions 254, 256, 260 or 262. As noted above, the buriedregions and the emitter region of the counterpart overvoltage protectiondevice are similarly constructed.

[0085] In the subsequent processing stages of the device 250, a trench290 is formed through the second base region 276 for electricallyisolating the buried region 260 from the adjacent portion of the secondbase region 276. The shape of the trench 290 is a partial circularshape, concentric with the frustoconical-shaped buried region, such asshown in FIG. 16. A similar trench 292 is formed through the second baseregion 276 for providing electrical isolation from the respective buriedregion 262. The trenches 290 and 292 are then filled with a standardleadaluminoborosilicate glass insulating material. The function of theglass-filled trenches 290 and 292 is for forcing the conduction ofcarriers from the buried regions 260 and 262 to the emitter 258, ratherthan to a metal contact (not shown) via the second base region 276. Withthis construction, the carriers generated by the buried region 260 favora conduction path in the heavily-doped portion of the second base region276 located adjacent to the emitter 258, rather than through thelightly-doped first base region 268 under the glass-filled trenches 290and 292 to the second base region 276. Stated another way, were it notfor the glass-filled trenches 290 and 292 located as shown, the carriersemitted from the buried regions 260 and 262 would be short circuiteddirectly through the second base region 276 to the corresponding contact(not shown), rather than be carried to the emitter 258. The glass-filledtrench 293 formed on the opposite side of the device 250 function toprovide the same advantage for the other overvoltage protection device.

[0086] The devices 250 formed on the semiconductor wafer are separatedfrom each other by a grid network formed in the opposing sides of thesemiconductor material. The grid network is filled with the glassinsulating material, which provides a protective passivation layer tothe side edges of the chip.

[0087] Before being scribed and broken into the individual devices 250,the wafer is masked to define metal contact areas. The overvoltageprotection devices of the invention have only a cathode contact on oneside, and an anode contact on the other side. Once masked, a metal isdeposited so as to form a contact on each side of the chip. The shape ofthe contacts on one side of the chip is shown in FIG. 19. Illustrated isa top contact 300 coated with a solder material. A corresponding bottomcontact is formed in a mirror image of that shown in FIG. 19. Thecontacts 300 do not overlie the buried regions, and the peripheral gridnetwork is shown providing electrical isolation between the centerburied regions 260 and 262 and the second base region (not shown).

[0088] A device formed according to the foregoing provides anovervoltage protection device characterized by a breakover voltage(V_(B0)) of about 10 volts and a device capacitance of about 60 pf.

[0089]FIG. 20. shows in diagrammatic form the patterns of carriers asemanating from each of the buried regions during initial turn on of oneovervoltage protection device, it being realized that the same type ofaction occurs with the counterpart overvoltage protection device. Thecircular-shaped buried regions influence corresponding circular areaswhere carriers travel outwardly to the surface of the emitter 258. Ascan be seen, a major portion of the surface of the emitter 258 receivesthe carriers and is thus involved during the turn on of the overvoltageprotection device. With a larger surface area of the emitter activeduring turn on, a higher surge current can be handled, and thus lessvoltage overshoot reaches the circuits to be protected. A more detaileddiscussion of the advantages of the plural buried regions spaced aroundthe emitter region is set forth below in conjunction with FIG. 24.

[0090] FIGS. 21-24 illustrate yet another embodiment of the invention.Here, the device 310 is formed on a square semiconductor chip having anarea of 105 mils square. The larger area device has a higher currentcarrying capability. With this increased semiconductor area (as comparedto the FIGS. 16-20 embodiment), an additional buried region is employed.Three buried regions 312, 314 and 316 are formed near the edge of thedevice 310, while two other buried regions 318 and 320 are formed nearthe center of the chip. Corresponding buried regions (not shown) areformed in mirror image locations on the bottom side of the chip. Theburied regions are located at the apexes of respective imaginarytriangles. In other words, buried regions 312, 314 and 318 are formed atthe apexes of a first triangle; buried regions 318, 314 and 320 areformed at the apexes of a second triangle; and buried regions 314, 316and 320 are located at the apexes of a third triangle. The breakdownjunctions of the buried regions 312 and 316 are laterally offset fromrespective comers of the emitter region 332. As will be described below,this positioning of the buried regions with respect to the emitterregion 332 facilitates a high-speed turn-on characteristic of the device310.

[0091] The various semiconductor regions of the device 310 are otherwiseformed in a manner substantially the same as that described above inconnection with FIGS. 16-20. The mid-region of the device 310 isidentified as reference numeral 322 in the cross-sectional view of FIGS.22 and 23. The buried regions of the device 310 are identified in FIG.22 as reference numerals 314 for a top buried region and 324 for abottom buried region. The device 310 of FIG. 23, when viewed along across-sectional view of line 23-23 of FIG. 21, illustrates a top buriedregion 320 and a bottom buried region 326. The first base region formedof a lightly doped N-type material is identified as reference numeral328. The first base region formed in the bottom surface of the chip andassociated with the counterpart overvoltage protection device isidentified as reference numeral 330. The n-wells are identified asreference numerals 333 and 334. The more heavily doped second baseregions are identified as reference numerals 326 and 328. The top P-typeemitter is identified by reference numeral 332, and the bottom P-typeemitter is identified by reference numeral 334. The electricallyisolating glass-filled trenches are shown as reference characters 336and 338.

[0092] While the embodiments of the invention shown in FIGS. 16-24 areillustrated with plural buried regions spaced around the peripheral edgeof the respective emitter regions, additional buried regions could alsobe formed under central circular openings formed through the emitters.Also, while it has been found that circular-shaped buried regions of aspecified diameter exhibit less device capacitance, as compared tocross-sectionally square-shaped buried regions of comparable widths,other shapes of the buried regions can be used. Indeed, the device canbe fabricated using some buried regions of one cross-sectional shape,and other buried regions located at other areas (such as comers) can befabricated with different cross-sectional shapes. While the utilizationof square or rectangular-shaped buried regions may provide a bettercoverage of the emitter area with carriers, with fewer areas void ofcarriers during initial turn on, the use of such shape is believed torepresent only a nominal increase in the turn-on speed of the device,with a corresponding disadvantage of higher device capacitance. As willbe set forth more fully below, the pattern by which carriers are emittedfrom the buried regions is generally similar to the cross-sectionalshape of the buried regions employed.

[0093] As noted above, the function of the buried regions is tofacilitate the initial turn on of a low breakover voltage device, whileyet maintaining a low capacitance. In order to accomplish this, and toreduce or eliminate “bottle-necking” of the current during turn on, itis desirable to form the buried regions in a spaced-apart manner so thatthe carriers emitted therefrom are distributed over a wide area, therebyallowing a large area of the emitter to become quickly functional andeffect a high current turn on of the device. As is well known, turn onof the overvoltage protection device is initiated by the currentcarriers flowing from the highly conductive buried regions to theemitter region, whereupon the emitter junction becomes forward biasedand thereafter device conduction occurs in the semiconductor regionsoutside of the buried regions. A high current turn on is achieved byforming the buried regions in a specified shape, and by positioning theburied regions around the emitter region. In other words, and as shownin FIG. 24, the buried regions 312-320 are formed in a cross-sectionallycircular shape to provide corresponding circular patterns or areas inwhich the carriers migrate during turn on. The buried region 312 isformed adjacent and laterally offset from a corner portion of theemitter region 332. In like manner, the buried region 316 is formedadjacent another corner of the emitter region 332, and laterally offsettherefrom. The buried region 314 is formed in a location intermediatethe comer buried regions 312 and 316. The pattern by which carriers areemitted from the buried region 312 are shown by broken lines 340. As canbe seen, the upper right comer portion of the emitter region 332 isprovided with carriers for initiating turn off of the device. The middleburied region 314 produces a pattern in a semi-circular area identifiedby broken lines 342. Much like the pattern 340 generated by thecorner-located buried region 312, the buried region 316 generates aquarter-circle pattern 344. The carrier patterns 340 and 342, and thecarrier patterns 342 and 344, each overlap somewhat. The remaining twoburied regions 318 and 320 generate corresponding semi-circular patterns346 and 348 which also overlap somewhat. The peripheral areas of carrierpatterns 346 and 348 are generally contiguous with the other carrierpatterns 340, 342 and 344. As can be appreciated, the concentration ofcarriers decreases as a function of distance from the buried regions.While there may exist a few areas under the emitter region 332, such asarea 350, that receive fewer carriers than the other emitter areas,substantially the entire area of the emitter region 332 is provided withcarriers generated from the various buried regions. Full turn on of thedevice 310 can thus be initiated in a high speed manner. Thissubstantially reduces bottle-necking of the current and allows hightransient currents to be accommodated by the device 310.

[0094]FIGS. 25 and 26 depict yet another embodiment of the overvoltageprotection device 360 constructed according to the principles andconcepts of the invention. This device is preferably constructed on achip having an area of 75 mils square. The device is formed with aP-type mid-region 362. Formed in both surfaces of the chip are a pair ofP-type buried regions. The overvoltage protection device formed in thetop surface of the chip is formed with two buried regions 364 and 366.The overvoltage protection device formed in the bottom surface of thechip also has two buried regions, one shown as reference numeral 368.Diffused in both the top and bottom surfaces of the chip are respectivelightly-doped N-type first base regions 370 and 372, and correspondingn-wells 373 and 376. The heavily doped N-type second base regions 378and 380 are formed in the respective lightly doped first base regions370 and 372. A top surface emitter region 382 is formed in the secondbase region 378, and a bottom surface emitter 384 is formed in thecorresponding second base region 380. The various processing stepsdescribed above in connection with the embodiments of FIGS. 16-24 can beused in forming the device of FIGS. 25-27.

[0095] In accordance with an important feature of the invention, theemitter region 382 has formed therein a pair of circular-shaped openings386 and 388. Formed adjacent to and laterally offset from the annularedges of the openings 386 and 388 are the respective breakdown junctions390 and 392. Each buried region 366 and 368 is formed so as to becentered about an axis extending through the respective emitter regionopenings 386 and 388. Moreover, the buried regions 366 and 368 areformed with circular-shaped breakdown junctions 390 and 392. The buriedregions are formed in the other surface of the chip in a similar mannerwith respect to openings in the emitter region 384. As noted above, thecircular-shaped breakdown junctions of the buried regions permits thedevice to be constructed with a small capacitance.

[0096] As can be seen from FIG. 25, each buried region 366 and 366 isformed generally centered in a half section of the emitter region 382.The carriers emitted from the breakdown junctions 390 and 392 thus allowa large surface area of the emitter region to become forward biasedduring initial turn on of the device 360. The emanation of the carriersfrom the breakdown junctions 390 and 392 is illustrated in FIG. 27. Itcan be seen that with this construction of the overvoltage protectiondevice 360, the overall capacitance is small due to the use of only twoburied regions per overvoltage protection device, and a high-speed turnon is achieved. While FIGS. 25-27 illustrate an embodiment where theemitter region is formed with plural openings therein, those skilled inthe art may find that the principles of the invention can be employed inconstructing a similar device having an emitter with a centrally-locatedemitter opening. A buried region would be located under the centralopening to provide carriers to a wide area of the emitter.

[0097] As noted above, a low capacitance overvoltage protection devicecan be used for protecting lines carrying high speed signals. Becausethe buried regions necessarily involve the use of heavily doped regionsto achieve a low breakdown voltage, such a structure also involves alarger capacitance. This is because with high concentration P-type andN-type junctions, the depletion region therebetween is small, thuspresenting a high capacitance structure. The high concentration buriedregions together with the high concentration second base regions formrespective breakdown junctions characterized with a relatively highcapacitance. In order to minimize the overall capacitance of the device,a small-area junction is formed in connection with each buried region,and plural buried regions are used. This structure not only reducescapacitance, but also provides a mechanism for distributing carriers toa large surface area of the emitter region during turn on.

[0098] From the foregoing, numerous embodiments of the invention havebeen disclosed. In any of the embodiments, a breakover voltage of thedevice can be achieved sufficiently low for protecting TTL digital orother low voltage analog or digital lines, and the like. In addition,other equipment susceptible to extraneous high voltages can be protectedwith the described overvoltage protection devices. A commoncharacteristic of each of the devices is that the buried region islaterally offset and adjacent to the emitter region so that the positionof the breakdownjunction of the buried region is independent of thedistance between the emitter-base junction and the base-mid-regionjunction. Stated another way, with these designs, the breakover voltageis independent of the holding current of the device. By utilizing buriedregions one over the other in bidirectional overvoltage protectiondevices, an economy of semiconductor area is realized. The utilizationof metal contact area placement in conjunction with the lead framesallows self-registration between the elements during the reflow solderassembly process.

[0099] While the preferred and other embodiments of the invention havebeen disclosed with reference to specific semiconductor techniques andmethods of operation, it is to be understood that changes in detail maybe made as a matter of design choices, without departing from the spiritand scope of the invention, as defined by the appended claims. Forexample, the devices may be fabricated utilizing impurities of theopposite type, other than those disclosed above.

What is claimed is:
 1. A bidirectional overvoltage protection device,comprising: a first group of semiconductor regions formed in asemiconductor chip for carrying current in response to a positivepolarity voltage applied across the device; a second group ofsemiconductor regions formed in the semiconductor chip for carryingcurrent in response to a negative polarity voltage applied across thedevice; and at least one buried region formed in association with eachsaid first and second group of semiconductor regions, said buriedregions being formed to define a breakover voltage for said overvoltageprotection device, and formed centrally and laterally between twoopposite sides of said semiconductor chip.
 2. The bidirectionalovervoltage protection device of claim 1, further including an emitterregion associated with each said first and second group of semiconductorregions, and wherein said buried regions are formed laterally offsetfrom the respective emitter regions.
 3. The bidirectional overvoltageprotection device of claim 1 or 2, wherein said semiconductor chip isformed with an anode and cathode contact for said first group ofsemiconductor regions, and a different anode and cathode contact forsaid second group of semiconductor regions.
 4. The bidirectionalovervoltage protection device of claim 3, wherein said semiconductorchip is formed having an anode and contact cathode on one surfacethereof, and the different anode and contact cathode on an opposite sidesurface of the semiconductor chip.
 5. The bidirectional overvoltageprotection device of claim 4, wherein the anode and cathode contacts onone side of said semiconductor chip define different contacts that areshort circuited together by a lead frame.
 6. The bidirectionalovervoltage protection device of claim 3, further including incombination atop lead frame soldered to a top pair of contacts defininga first set of anode and cathode contacts, and a bottom lead framesoldered to a pair of contacts defining a second set of anode andcathode contacts.
 7. The bidirectional overvoltage protection device ofclaim 1, 2 or 3, wherein there is formed in one surface of saidsemiconductor chip at least one first base region and said emitterformed thereover, at least one second base region laterally spaced fromsaid first base region, and a buried region formed between said firstand second base regions.
 8. The bidirectional overvoltage protectiondevice of claim 7, further including a PN junction between said buriedregion and said second base region, and including an electricallyisolating material formed down into said junction to prevent currentflow between said buried region and said second base region.
 9. Thebidirectional overvoltage protection device of claim 1, wherein saidsecond group of semiconductor regions are formed substantially identicalto said first group of semiconductor regions, said first and secondgroups of semiconductor regions being formed in opposite faces of saidsemiconductor chip.
 10. The bidirectional overvoltage protection deviceof claim 7, further including a first metal contact electricallyconnected to said emitter, and a second metal contact electricallyconnected to said first base region, said first and second metalcontacts being of substantially the same area when viewed from a topview.
 11. The bidirectional overvoltage protection device of claim 1 or2, further including: a buried region formed in one surface of saidsemiconductor chip, and a second buried region formed in an opposingsurface of said semiconductor chip, and wherein said first and secondburied regions are formed vertically aligned with each other.
 12. Anovervoltage protection device, comprising: at least one base regionformed in a semiconductor material; an emitter region formed in saidbase region such that abase-emitter junction is formed, said emitterregion defined by a peripheral lateral boundary; a plurality of buriedregions for promoting current flow through said device during turn on,said buried regions formed with a breakdown junction for establishing abreakover voltage of said device; and at least a portion of said buriedregions each being laterally offset from said emitter region.
 13. Theovervoltage protection device of claim 12, wherein said buried regionsinclude buried regions spaced around the peripheral lateral boundary ofsaid emitter region so that carriers emitted from said buried regionsare collected by substantially an entire surface of said emitter region.14. The overvoltage protection device of claim 12 or 13, wherein saidemitter region includes at least one opening therein, said openingbounded by a circular edge, and one said buried region is axiallyregistered with said opening in said emitter region.
 15. The overvoltageprotection device of claim 12 or 13, wherein said emitter region isformed with at least two comers, and further including at least two saidburied regions formed laterally adjacent respective said comers of saidemitter region.
 16. The overvoltage protection device of claim 12, 13 or14, wherein said buried regions are formed using a mask having generallycircular openings therein such that said buried regions have a generallycircular profile.
 17. The overvoltage protection device of claim 12, 13,14, 15 or 16, wherein said emitter region is formed with at least oneindented area formed laterally in said peripheral boundary, and one saidburied region is located so as to be laterally adjacent said indentedarea.
 18. The overvoltage protection device of claim 14, wherein saidindented area has a shape substantially the same as a shape of a portionof said buried region located adjacent thereto.
 19. The overvoltageprotection device of claim 12, further including an electrical isolationdisposed between at least a portion of said base region and one saidburied region to prevent current flow between a portion of said baseregion and said buried region.
 20. The overvoltage protection device ofclaim 19, wherein said electrical isolation comprises a trench formed insaid base region and filled with an electrical insulating material. 21.The overvoltage protection device of claim 12, wherein said base regioncomprises a first base region having an impurity concentration of aspecified level having an impurity concentration greater than that ofsaid first base region.
 22. The overvoltage protection device of claim21, wherein said first base region is formed having a well with alateral shape that is generally the same as a lateral shape of saidemitter region.
 23. The overvoltage protection device of claim 12,further including an electrical isolation isolating at least a portionof one said buried region from at least a portion of said base region.24. An overvoltage protection device, comprising: at least one baseregion formed in a semiconductor material; an emitter region formed insaid base region such that abase-emitter junction is formed, saidemitter region having at least one opening therein bounded by a closedperipheral edge; at least one buried region forming a breakdown junctionwith said base region, said breakdown junction being axially registeredwithin said opening in said emitter region, and said breakdown junctionbeing laterally offset from said closed peripheral edge.
 25. Theovervoltage protection device of claim 24, further including plural saidopenings, and further including a plurality of said buried regions, eachburied region having a breakdown junction axially aligned and laterallyoffset with a respective said emitter opening.